Neorv32 synthesis in Design compiler
mahdi259 opened this issue · comments
Hi,
This is actually a question. I have synthesized Neorv32 in Design Compiler. My problem is with the resulting design file that I produce with design compiler. It actually gives 'X' signal in simulation for some outputs. Have you ever synthesized Neorv32 in Design compiler @stnolting?
Thanks
You mean Synopsys Desgin Compiler?
Unfortunately, I have never used that...
It actually gives 'X' signal in simulation for some outputs.
Which signals are we talking about?
Can you see the core doing anything useful, e.g. booting up?
Yes, I synthesized the same neorv32_top that I used in neorv32_tb_simple. The UART signals are getting 'X'. If I solve it, I will describe the issue here.
The problem was with hold time of implementation. I relaxed the constraints and it worked.
Great to hear! 👍
Hi @stnolting
Do you have a friend that is familiar with synopsis DC?
Unfortunately not. 🙈
But maybe someone else here can help?!
Ok thanks
For anyone who reads this later. Generating sdf file of synthesized design and using it for simulation in Questasim improves maximum operational frequency of design.