Steven (stevenadsouza)

stevenadsouza

Geek Repo

Location:Pune, Maharashtra, India

Home Page:https://www.linkedin.com/in/stevenadsouza/

Twitter:@stevenadsouza

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Steven's starred repositories

llm.c

LLM training in simple, raw C/CUDA

Language:CudaLicense:MITStargazers:22666Issues:0Issues:0

assembler-simulator

Simple 8-bit Assembler Simulator with Angular.js

Language:JavaScriptStargazers:960Issues:0Issues:0

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Language:CLicense:NOASSERTIONStargazers:230Issues:0Issues:0

icestation-32

Compact FPGA game console

Language:VerilogLicense:MITStargazers:149Issues:0Issues:0

awk

One true awk

Language:CLicense:NOASSERTIONStargazers:1965Issues:0Issues:0

PearlRiver

1st Testwafer for LibreSilicon

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lsc

Libre Silicon Compiler

Language:HaskellStargazers:22Issues:0Issues:0

tinygpus

TinyGPUs, making graphics hardware for 1990s games

Language:LuaLicense:GPL-3.0Stargazers:95Issues:0Issues:0

DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Language:VerilogLicense:Apache-2.0Stargazers:129Issues:0Issues:0

pmu-tools

Intel PMU profiling tools

Language:PythonLicense:GPL-2.0Stargazers:1977Issues:0Issues:0

open-gpu-kernel-modules

NVIDIA Linux open GPU kernel module source

Language:CLicense:NOASSERTIONStargazers:14939Issues:0Issues:0

MainboardTerminal

A Retro-style Computer with a Modern Core

License:MITStargazers:770Issues:0Issues:0

Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Language:C++License:NOASSERTIONStargazers:1273Issues:0Issues:0

geogram

a programming library with geometric algorithms

Language:C++License:NOASSERTIONStargazers:1784Issues:0Issues:0

moto

A library that allows you to easily mock out tests based on AWS infrastructure.

Language:PythonLicense:Apache-2.0Stargazers:7555Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:1170Issues:0Issues:0

libusb

A cross-platform library to access USB devices

Language:CLicense:LGPL-2.1Stargazers:5153Issues:0Issues:0

litex

Build your hardware, easily!

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VerilogBoy

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Language:VerilogLicense:NOASSERTIONStargazers:451Issues:0Issues:0

vcdrom

VCD viewer

Language:JavaScriptLicense:MITStargazers:78Issues:0Issues:0

openc906

OpenXuantie - OpenC906 Core

Language:VerilogLicense:Apache-2.0Stargazers:310Issues:0Issues:0

qtrvsim

RISC-V CPU simulator for education purposes

Language:C++License:GPL-3.0Stargazers:459Issues:0Issues:0

OBJEX_LINK

OBJEX Link is a modular IoT board. It is designed to develop IoT devices that are easy to repair and recycle. It is also perfect for rapid prototyping and developing research and robotics projects.

Language:C++License:NOASSERTIONStargazers:106Issues:0Issues:0

OpenLane

This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Language:PythonLicense:Apache-2.0Stargazers:139Issues:0Issues:0

macSVG

macSVG - An open-source macOS app for designing HTML5 SVG (Scalable Vector Graphics) art and animation with a WebKit web view ➤➤➤

Language:Objective-CLicense:NOASSERTIONStargazers:1152Issues:0Issues:0

watchysim

Simulation framework for Watchy watch faces

Language:CLicense:MITStargazers:83Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:10Issues:0Issues:0

xuantie-gnu-toolchain

GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……

Language:CLicense:NOASSERTIONStargazers:87Issues:0Issues:0

projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

Language:SystemVerilogLicense:MITStargazers:557Issues:0Issues:0

corescore

CoreScore

Language:VerilogLicense:Apache-2.0Stargazers:135Issues:0Issues:0