Bug: accessing parameters by upward hierarchial name

[H. Peter Anvin]

Accessing parameters by upward-looking hierarchical name seems to always return the value as specified in alphabetically first(!) instance of the module in question.

This is tested with the vlog95 backend; I don't know if it is backend specific.

To test, compile the included example:

iverilog -g2012 -s main -t vlog95 -o inherit.v95 inherit.sv

... and observe the output definition of module "ab".

One would instead expect "main.mybc[01x]"
to have different expansions in their respective instantiations of "ab".

iverilog -v
Icarus Verilog version 12.0 (stable) ()

Files (with .txt added due to github drain bramage):

inherit.sv.txt
inherit.v95.txt

[martinwhitaker]

This does seem to be backend-specific. With this simplified example:

module b (output b);
   assign b = c.foo; 
endmodule

module c #(parameter foo = 1'b1) (output b);
   b my_b (.b(b));
endmodule

module main();
   wire bx, b0, b1;
   
   c #(.foo(1'bx)) my_cx (.b(bx));
   c #(.foo(1'b0)) my_c0 (.b(b0));
   c #(.foo(1'b1)) my_c1 (.b(b1));

   initial #0 $display(bx,,b0,,b1);
endmodule

I get

% iverilog br_gh1108.v && a.out
x 0 1
% iverilog -tvlog95 -o tmp.v br_gh1108.v && iverilog tmp.v && a.out
0 0 0