steveicarus / iverilog

Icarus Verilog

Home Page:https://steveicarus.github.io/iverilog/

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Undetected error when a whole array is both procedurally and continuously assigned.

martinwhitaker opened this issue · comments

This code should be rejected:

module test();

logic [7:0] p[1:0];
logic [7:0] q[1:0];

assign q = p;

initial q = '{ 0, 0 };

endmodule

Similarly if q is connected to a module output port.

This is now fixed in the master branch.