stevehoover

LF-Building-a-RISC-V-CPU-Core

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

RISC-V_MYTH_Workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

makerchip_examples

LF-Building-a-RISC-V-CPU-Core-Course

The Linux Foundation/Redwood EDA "Building a RISC-V CPU" Course content, also available via EdX.

1st-CLaaS

Developing Smith Waterman accelerators on F1 instances using 1st CLaaS

immutable

warp-v_includes

A companion to /warp-v containing files that are included from /warp-v.

conversion-to-TLV

A repository for exploring LLM-assisted code conversion to TL-Verilog.

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

test

hooo

tt05-verilog-demo

Verilog Demo, updated for Tiny Tapeout 05

chips-gsoc-ideas

efabless-tt-fpga-dl-demo-AES

efabless-tt06-verilog-template

fossi-foundation-web

fossi-foundation.github.io

FOSSi Foundation Website

makerchip_sorting_network

The sorting network example from Makerchip, saved for Community Platform.

MEST_Course

Content for MEST circuit design course.

moku_tlv_lib

TL-Verilog content for Liquid Instruments Moku products.

tlv-vscode

tt-fpga-demo

tt-fpga-hdl-demo

tt-fpga-hdl-demo-tmp-test

Temporary -- DELETE ME

tt-fpga-hdl-demo2

tt-mest-fpga-wokwi-template

tt06-my-proj

tt06-tl-verilog-template

Submission template for Tiny Tapeout 06 - Verilog HDL Projects

tt07-my-tl-verilog-project

tt08-makerchip-template

Submission template for Tiny Tapeout 7 with a "makerchip" branch supporting Makerchip virtual lab and TL-Verilog