soobaanvlsi

Fooocus

Focus on prompting and generating

100DaysOfRTL

100 Days of RTL

Asynchronous-FIFO

An FPGA implementation of Cummings' Asynchronous FIFO

awesome-iggly

A curated list of awesome warez and piracy links

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

hbird-sdk

OpenSource HummingBird RISC-V Software Development Kit

riscv-tests

riscv-test-env

e200_opensource

The Ultra-Low Power RISC Core

e203_hbirdv2

The Ultra-Low Power RISC-V Core

tinyriscv

A very simple and easy to understand RISC-V core.

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

minerva

A 32-bit RISC-V soft processor

riscv-formal

RISC-V Formal Verification Framework

github-flash1

UART

UART design in SV and verification using UVM and SV

Absolute-Value-Finder

finding the Absolute Value

ahb2apb_bridge_vip

AHB to APB Bridge VIP

AMBA_AXI3

System Verilog and Emulation. Written all the five channels.

cic_core

CIC-filter core