slaclab / surf

A huge VHDL library for FPGA development

slaclab/surf Issues

Wrong signal assigment
Closed 9 months ago1
help with Tcl command using Ruckus
Closed a year ago2
Error in FifoMux.vhd when RD_DATA_WIDTH_G < WR_DATA_WIDTH_G and rd_en is a pulse
Closed 2 years ago1
Changes to base/ram/ruckus.tcl in v2.31.1 incorrectly prevents builds with XPM true dual port FIFO using Vivado 2019.1
Closed 2 years ago3
use surf in a project
Closed 3 years ago3
Inferred AxiDualPortRam XPM synth mode fails
Closed 3 years ago1
distribured AxiDualPortRam latency wrong
Closed 3 years ago1
AXI4-Lite Xbar decoder error response violates protocol rules
Closed 4 years ago6
SlvDelayFifo wraparound
Closed 4 years ago1
adc32rf45.vhd width mismatch
Closed 4 years ago2
Pgp3GthUsWrapper.vhd SYNTH_MODE_G not declared
Closed 4 years ago1
How can i build a example project?
Closed 5 years ago4
GTX7 RXCHBONDSLAVE and Clock Correction
Closed 7 years ago2