sjalloq

cocotb-regfile

An example testbench around an open-register-design-tool generated register file

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

.emacs.d

buildbot

Python-based continuous integration testing framework; your pull requests are more than welcome!

caravel

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

components

Library of components for Circuit Diagram.

dali-master

Mbed implementation of a Dali master

dali-pigpio

A Dali implementation using the Raspberry Pi and the Python PiGPIO library

edalize

An abstraction library for interfacing EDA tools

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

i2c

I2C controller core

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

jinja2verilog

kicad-footprint-generator

creating kicad footprints using python scripts

kicad-footprints

Official KiCad Footprint Libraries for the future Kicad version 5

kicad-symbols

Official KiCad schematic symbol libraries for the future Kicad 5 release

kicad-templates

KiCad project templates

mbed_poe

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

opentitan

OpenTitan: Open source silicon root of trust

orbuculum

Cortex M SWO SWV Demux and Postprocess (Software)

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

python-dali

Library for controlling DALI lighting systems

rpi-bc_dali

A Dali expander board for the Phoenix RPI-BC case.

serv

SERV - The SErial RISC-V CPU

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

uvm-python

UVM 1.2 port to Python

yosys

Yosys Open SYnthesis Suite