This project implements real-time audio processing using a Basys-3 FPGA board and a Pmod I2S2 digital audio interface. The audio processing is performed using low-pass, high-pass, band-pass, and moving average FIR filters.
Video Demonstration: Real-time Audio Processing via FIR Filters on Basys-3 FPGA
- Basys-3 FPGA board
- Pmod I2S2 digital audio interface
- GNU Octave or MATLAB for generating filter coefficients using the
filter_gen.m
script. - Vivado Design Suite for synthesizing and implementing the FPGA design.
Baysys-3-Master.xdc
: Constraints file for the Basys-3 FPGA board.fir_backend.sv
: Implementation of a single/dual channel FIR filter backend.fir.sv
: Handles and connects the AXI stream to FIR filter backendfilter_gen.m
: MATLAB/Octave script to generate hexadecimal coefficients for a desired FIR filtersingle_channel_fir_engine_tb.sv
anddual_channel_fir_engine_tb.sv
: Testbenches for testing the FIR filter backend implementations.
- Generate filter coefficients using the
filter_gen.m
script in MATLAB or Octave. - Open Vivado Design Suite and create a new project.
- Add the required files to the project and synthesize the design.
- Run the testbench to verify the functionality of the FIR filters.
- Connect the Pmod I2S2 digital audio interface to the FPGA on JA.
- Implement the design on the Basys-3 FPGA board.
The performance of the FIR filters may be limited by the kernel length and the number of filter taps. A longer kernel length would result in better performance, but may require a larger FPGA or a more powerful processor to handle the increased computation, or a more sophisticated design.
This project demonstrates the ability to implement real-time audio processing using FIR filters on a Basys-3 FPGA board and a Pmod I2S2 digital audio interface. The provided files and instructions should provide a starting point for further experimentation and customization of the audio processing capabilities.
- Digilent/Pmod-I2S2 GitHub Project
- Practical FIR Filter Design
- My favorite AXI Stream Tutorial