simpsoneric

genode-manual

Reference manual for the Genode OS Framework

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

OpenSK

OpenSK is an open-source implementation for security keys written in Rust that supports both FIDO U2F and FIDO2 standards.

bbqueue

A SPSC, lockless, no_std, thread safe, queue, based on BipBuffers

ethernet-fmc-axi-eth

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

adoc-presentation-model

SYNCHRONIZED FROM GITLAB. A full AsciiDoc extended example generating both HTML PDF and Reveal.js slides #asciidoctor #plantuml #reveal

bytefield-svg

Node module that generates byte field diagrams in SVG format

riscv-cocotb

cocotb infrastructure for RISC-V core testing

CocotbLib

snickerdoodle-hls-data-mover

A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits)

Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

awesome-hdl

Hardware Description Languages

dandelion-lib

A dataflow library for TAPAS and dandelion projects

computer-architecture-and-systems-resources

A curated list of Computer Architecture and Systems resources

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

fusesoc-cores

FuseSoC standard core library

ariane

Ariane is a 6-stage RISC-V CPU

hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

rapid-design-methods-for-developing-hardware-accelerators

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

surf

A huge VHDL library for FPGA development

ruckus

Vivado build system

logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

hdl_checker

Repurposing existing HDL tools to help writing better code

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

cluelib

A generic class library in SystemVerilog

hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

matchlib

SystemC/C++ library of commonly-used hardware functions and components for HLS.