Henrik Fegran's repositories
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Ada_Drivers_Library
Ada source code and complete sample GNAT projects for selected bare-board platforms supported by GNAT.
Language:AdaBSD-3-Clause000
core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Language:MakefileNOASSERTION000
cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
Language:SystemVerilogNOASSERTION000
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
Language:SystemVerilogNOASSERTION000
cv32e40x-dv
CV32E40X Design-Verification environment
Language:AssemblyNOASSERTION000
debug
Debug
000
force-riscv
Instruction Set Generator initially contributed by Futurewei
Language:C++NOASSERTION000
Language:AssemblyBSD-3-Clause000
riscv-dv
Random instruction generator for RISC-V processor verification
Language:PythonApache-2.0000
tinyusb
An open source cross-platform USB stack for embedded system
Language:CMIT000
usb_embedded
An Ada USB stack for embedded devices
Language:AdaBSD-3-Clause000