Chaitanya Kunda's repositories
100-DAYS-OF-RTL
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
Language:Verilog000
100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Language:VerilogApache-2.0000
Language:Verilog000
Language:VerilogCERN-OHL-S-2.0000
Language:VerilogApache-2.0000