Signature IP Corporation's repositories
SD_AXIS_traffic_generator
Software defined cycle accurate AXI Stream traffic generator
antlr4_system_verilog_parser
ANTLR4 grammar and parsing utilities for System Verilog 2017 (full support)
cycle-accurate-SystemC-simulator-over-ramulator
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
DEF-Parser
Design Exchange Format (DEF) parser toolkit copy. Cadence open-source parsers for DEF
LAP
Lark based DEF file parser
ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
verilator
Verilator open-source SystemVerilog simulator and lint system
X6
🚀 JavaScript diagramming library that uses SVG and HTML for rendering.
logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.