葉舜良's starred repositories
PH-Experiment
大二上学期--计算机组成与设计(PH)--实验
NyuziProcessor
GPGPU microprocessor architecture
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
basic_verilog
Must-have verilog systemverilog modules
verilog-fifo
pipelined verilog fifo
Architecture-of-Parallel-Computers
Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid
Literatures-on-GNN-Acceleration
A reading list for deep graph learning acceleration.
A-Single-Path-Delay-32-Point-FFT-Processor
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
MakeNTU2019_workshop
MakeNTU 2019 workshop tutorial for Face Lock with RPi, Azure, OpenCV.
Efficient-Deep-Learning
Collection of recent methods on (deep) neural network compression and acceleration.
GNN-hardware-acceleration-paper
This repo is to collect the state-of-the-art GNN hardware acceleration paper
GoodTestbench
Make Verilog great again, hopefully.
GCN-Inference-Acceleration-HLS
An end-to-end GCN inference accelerator written in HLS
Systolic-Array-for-Smith-Waterman
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
Cyclone_II_SoPC
VHDL hardware accelerators on Cyclone II FPGA with MCU apps in C for Nios II core
style-guides
lowRISC Style Guides
High-Performance-Computing-Lab
All experiments performed as part of CEE82A - High Performance Computing.