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xls

XLS: Accelerated HW Synthesis

Language:C++Apache-2.0115800

Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Language:BluespecApache-2.034700

serv

SERV - The SErial RISC-V CPU

Language:VerilogISC133500

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

Language:VerilogApache-2.011600

Vitis-Tutorials

Vitis In-Depth Tutorials

Language:CMIT114900

hw

RTL, Cmodel, and testbench for NVDLA

Language:VerilogNOASSERTION167700

fpga-partial-reconfig

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

Language:SystemVerilogMIT8500

riscv-dv

Random instruction generator for RISC-V processor verification

Language:PythonApache-2.097800

libpku

贵校课程资料民间整理

Language:TeX3024400

Detectron

FAIR's research platform for object detection research, implementing popular algorithms like Mask R-CNN and RetinaNet.

Language:PythonApache-2.02621200

Embedded-Neural-Network

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

convolution_network_on_FPGA

CNN acceleration on virtex-7 FPGA with verilog HDL

Language:Verilog39200

CNN_FPGA

verilog CNN generator for FPGA

Language:V3200

NetFPGA-public

NetFPGA public repository

Open-Source-FPGA-Bitcoin-Miner

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

Language:VHDLGPL-3.0126500

tensorflow-windows-wheel

Tensorflow prebuilt binary for Windows

Language:Python364900

awesome-python-applications

💿 Free software that works great, and also happens to be open-source Python.

Language:Jupyter Notebook1644300

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogISC295600

verilog-ethernet

Verilog Ethernet components for FPGA implementation

Language:VerilogMIT202100

sw

NVDLA SW

Language:C++NOASSERTION47700

f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Language:CBSD-2-Clause40000

sha256

Hardware implementation of the SHA-256 cryptographic hash function

Language:VerilogBSD-2-Clause30800

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Language:AssemblyMIT235500

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Language:VHDLNOASSERTION149800