ESP-IDF version of FPGA config loader for Spartan Edge Accelerator Board
This is sample code on how to correctly parse a 7 Series bitstream and send it from the ESP32 down to the Spartan 7 Accelerator on the Seeed Studio Spartan Edge Accelerator Board (see https://www.seeedstudio.com/Spartan-Edge-Accelerator-Board-p-4261.html).
I had copied this over from a working version but have yet to test it in isolation. Hence, it should just serve as an example of how to do this and nothing more.