usc_vlsi_chip_project
RTL and verification files of EE577b, pipelined multi-core chip design with Network on Chip interconect. Dedicated CRC hardware accelerator built into the pipelined processor with corresponding instruction set.
RTL and verification files of EE577b, pipelined multi-core chip design with Network on Chip interconect. Dedicated CRC hardware accelerator built into the pipelined processor with corresponding instruction set.
GNU General Public License v3.0