Consider changing the default timescale

[Steven Herbst]

It looks like the default timescale (for Icarus at least) is 1s/1s. This can lead to some unusual results due to very low time resolution (e.g., a failure in the function test when trying to wait until a bit after a clock edge). I suggest we change to a default with higher resolution; two that I have commonly used are:

• 1ns/1ps (digital design)
• 1s/1ps (analog modeling)

Unfortunately this implementation of this feature would be simulator dependent. For example, with Icarus Verilog one needs to create a command file and then add a default timescale command (described here)

Thoughts on what a good default timescale would be and whether this would cause any issues?