sebinho

ces_util_lib

CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules

flatpak-python

Playing with Flatpak and Python

DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

vsd-physical-design-using-open-source-tools

The repository shows the 5 - day wrokshop for beginners using open source tools like yosys, magic, opentimer, qrouter and the purpose of this repository is to provide a complete idea about the 5 - days workshop on VLSI SoC/Physical design using open source EDA tools.

OpenLANE-SkyWater130-workshop

This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop helps to familiarise with the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm PDK.

lambdapdk

Library of open source Process Design Kits (PDKs)

huawei-solar-lib

Python library for communicating with Huawei SUN2000 inverters - mirror of https://gitlab.com/Emilv2/huawei-solar/

zerosoc

Demo SoC for SiliconCompiler.

switchboard

Communication framework for RTL simulation and emulation.

magic

Magic VLSI Layout Tool

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

ghdl-yosys-plugin

VHDL synthesis (based on ghdl)

yosys

Yosys Open SYnthesis Suite

siliconcompiler

A modular build system for hardware

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cocotbext-i2c

I2C models for cocotb

i3c-slave-design

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

verilog-i2c

Verilog I2C interface for FPGA implementation

corsair

Control and Status Register map generator for HDL projects

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

huawei_sun_mqtt

fuse-zynq

Generate Zynq configurations without using the vendor GUI

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

edalize

An abstraction library for interfacing EDA tools

cocotbext-uart

UART models for cocotb

core_dbg_bridge

UART -> AXI Bridge

surf

A huge VHDL library for FPGA development

cocotbext-axi

AXI interface modules for Cocotb

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development