Implementation of an Adaptive Median Filter in Verilog (Simulation only)
This project is an implementation of "Mukherjee, Manali, and Mausumi Maitra. "Reconfigurable architecture of adaptive median filter—An FPGA based approach for impulse noise suppression." Proceedings of the 2015 Third International Conference on Computer, Communication, Control and Information Technology (C3IT). IEEE, 2015.".
Other article used in this implementation: Rafael C. Gonzalez, and Richard E. woods, Digital Image Processing, 3rd edition, Prentice Hall,2009. Bates, Gavin L., and Saeid Nooshabadi. "FPGA implementation of a median filter." TENCON'97 Brisbane-Australia. Proceedings of IEEE TENCON'97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications (Cat. No. 97CH36162). Vol. 2. IEEE, 1997. Fahmy, Suhaib A., Peter YK Cheung, and Wayne Luk. "Novel FPGA-based implementation of median and weighted median filters for image processing." International Conference on Field Programmable Logic and Applications, 2005. IEEE, 2005. Prasad, Devi, et al. "Sorting networks on FPGA." Proceedings of the WSEAS International Conference on Telecommunications and Informatics (TELE-INFO). 2011.
- Create a project using files in the 'Verilog' folder in ModelSim
- Use Image2Hex_Converter to create input file (noisy image as hex file)
- Run Main.do script
- Use Image2Hex_Converter to open the output file and calculate results
