Rust Litex HAL
A Rust embedded HAL crate for LiteX cores. It contains basic HAL traits for GPIO, UART, SPI, and delay.
More info and instructions on my blog and example project in this repo
The repository also contains an example that you can run on Verilator using litex_sim.
Compiling and simulating the example
Compilation
The following dependencies are required to generate Rust code for peripherals (also called Peripheral Access Crate or PAC) and build the example for it.
Rust target for RISCV 32I
Our example use VexRiscv, so to be able to compile them you need to add riscv32i-unknown-none-elf target for Rust.
rustup target add riscv32i-unknown-none-elfPython
For LiteX scripts.
- ArchLinux:
sudo pacman -S python- Ubuntu:
sudo apt install python3- Universal LiteX script
LiteX
To build cores and optionally simulate it using verilator.
Simulation on litex_sim
The following dependencies are required if you want to run the example on litex_sim.
Cross compiler for RISCV 32I
To compile VexRiscv soft core. RISCV 64 can also build RISCV 32.
- ArchLinux:
sudo pacman -S riscv64-elf-gcc- Ubuntu:
sudo apt install gcc-riscv64-unknown-elfVerilator
Simulator to run simulation.
- ArchLinux:
sudo pacman -S verilator- Ubuntu:
sudo apt install verilatorLLVM tools
LLVM tools, needed to convert the example from ELF to BIN.
rustup component add llvm-tools-previewcargo-make
Rust task runner and build tool, needed to automate simulation.
- Cargo:
cargo install --no-default-features cargo-make- ArchLinux (from AUR):
paru -S cargo-makecargo-binutils
Cargo subcommands to invoke the LLVM tools, needed to convert the example from ELF to BIN.
- Cargo:
cargo install cargo-binutils- ArchLinux (from AUR):
paru -S cargo-binutilsSimulation
To run the simulation execute the following command:
cargo make simulate --example counterYou can pass additional Cargo flags such as --release at the end of the simulation command.