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sbourdeauducq / serdes-tdc

SERDES-based TDC core for Spartan-6

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Time to Digital Converter core for Spartan-6 FPGAs
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Directory organization:
   core/            VHDL sources of the TDC core.
   demo/            Demonstration design for the SPEC board.
   doc/             Documentation.
   hostif/          Optional host interface.

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SERDES-based TDC core for Spartan-6

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Language:Verilog 83.7%Language:C 12.6%Language:Assembly 1.8%Language:VHDL 1.8%Language:Python 0.1%Language:Objective-C 0.0%