Sathvik Swaminathan's repositories
Single-Cycle-RISC-V-Processor
Single Cycle Processor based on the RISC-V ISA. Supports R-type, lw, sw, and beq instructions.
COVID19-SIR-MODEL
SIR Model to predict the number of COVID-19 cases.
cs2200-vm-sim
Virtual Memory Simulator
5-stage-Pipelined-Processor-RISC-V
5 stage Pipelined Processor based on the RISC-V ISA implemented using TL-Verilog
cheribuild
Easily build and run CHERI related projects
covert-channel
Implementation of a cache covert channel that doesn't require threshold calibration
Image-Compression-SVD
Compressing Images by computing the SVD of the Image Matrix
ligra
Ligra: A Lightweight Graph Processing Framework for Shared Memory
Linear-Regression
Different ways of Implementing Linear Regression
nand2tetris
Solutions to Nand2Tetris Programming Assignments on Coursera
qemu
QEMU with support for CHERI
QKD-sim
Simulation of the BB84 and B92 protocol
ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
rars
RARS -- RISC-V Assembler and Runtime Simulator
sathvikswaminathan.github.io
Personal webpage
Sentiment-Analysis
Performing Sentiment Analysis by implementing the Naive Bayes Classifier
shell
Basic implementation of a shell
TVCSim
A simulator system for thrust vector controlling
UART-core
UART core equipped with FIFO buffer