AKASH SALOW's repositories
python-tutorials
PythonTutorials
CC3200-ili9341-LCD-display
CC3200 LCD/ TFT display ILI9341
CC3200-Ultrasonic-sensor-HC-Sr04
This project is to create a interface for HC SR04 from the CC3200 MCU by Texas instruments
CircleJump
Trying out Godot from the tutorial by KidsCanCode Youtube Playlist - https://youtu.be/wU6otgwaNQg
android-ndk
Android NDK samples with Android Studio
Artist-Theme
A free Jekyll theme
avsdbgp_3v3
This repository will keep the simulation files, steps and other relevant files in the development of Bandgap Reference IP for the EICT IITG-VSD summer online research internship 2020.
avsddac_3v3
This repository contains the design and simulation process and results of potentiometric digital to analog converter.
cc3200-ili9341
driver for ili9341 or ili9340 for CC3200 texas instruments written for code composer studio
html5test
Arcana Jekyll Theme - more themes available @ http://cloudcannon.com/jekyll_themes
Movie-Recommendation-System
Recommends movies and predicts ratings to an user for an item
Movie-Ticket-Booking
Languages Used: html,css,js,bootstrap,angularjs 1.7,java (Jersey Webservices)
On-board-sensors---cc3200
cc3200 on board sensors
openlane_build_script
This script builds openlane and all its dependencies on a Ubuntu (only) System.
Project
Start of android
siliconcompiler
SiliconCompiler is an open source build system that automates translation from source code to silicon.
Spiking-Neural-Network
Pure python implementation of SNN
synth
The latest code to make your own virtual sound synthesizer in Windows. Please see the videos associated with this code. Links in the source files.
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.