This repository contains Verilog code examples that demonstrate various functionalities and designs. Each module is implemented as a separate Verilog file.
This module converts a binary input into separate ASCII characters.
binary_input
(112 bits): Binary input data.
part_7790_0
topart_7790_15
(7 bits each): ASCII characters derived from the binary input.
This is a testbench module for the bintoascii
module. It provides stimulus to the module and displays the output ASCII characters.
binary_input
(112 bits): Binary input data.
part_7790_0
topart_7790_15
(7 bits each): ASCII characters derived from the binary input.
This module implements the Hamming code encoder for each of the 16 input parts.
part_7790_0
topart_7790_15
(7 bits each): Input data for each part.
out_77990_0
toout_77990_15
(11 bits each): Hamming code output for each part.