An instruction set simulator coded in C language, which mimics the behavior of a microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers.
A simple implementation of 7 Stage APEX Pipeline
Sagar Vishwakarma (svishwa2@binghamton.edu)
State University of New York, Binghamton
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This code is a simple implementation of 7 Stage APEX Pipeline. Fetch -> Decode -> Execute One -> Execute Two -> Memory One -> Memory Two -> Writeback
You can read, modify and build upon given codebase to add other features as required in project description. You are also free to write your own implementation from scratch.
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All the stages have latency of one cycle. There is a single functional unit in EX stage which perform all the arithmetic and logic operations.
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Logic to check data dependencies has been included.
- Makefile - You can edit as needed
- file_parser.c - Contains Functions to parse input file.
- cpu.c - Contains Implementation of APEX cpu.
- cpu.h - Contains various data structures declarations needed by 'cpu.c'.
- go to terminal, cd into project directory and type 'make' to compile project
- Run using ./apex_sim <input_file> <num_cycle> eg: ./apex_sim input.asm simulate 50
File : input_test_0.asm ---> 39 cycle (!Forwarding) till HALT instruction is processed in Writeback.
File : input_test_1.asm ---> 41 cycle (!Forwarding) till HALT instruction is processed in Writeback.
File : input_test_0.asm ---> 28 cycle (Forwarding) till HALT instruction is processed in Writeback.
File : input_test_1.asm ---> 27 cycle (Forwarding) till HALT instruction is processed in Writeback.