rust-embedded / riscv

Low level access to RISC-V processors

rust-embedded/riscv Issues

`riscv`: Consider strategy for exception safe code
Updated 7 days ago3
RFC: Platform-specific exception codes
Updated 14 days ago2
`riscv-rt`: Implement support for hardware interrupt dispatching
Closed 16 days ago5
`riscv`: Linking fails when using this crate as a dependency
Closed 17 days ago5
`riscv`: All the CSR write operations should be unsafe by default
Updated 18 days ago1
`riscv`: Pub macros for non-standard CSRs
Closed a month ago1
`riscv-rt`: link.x expected filename pattern
Closed a month ago1
`riscv`: Support more fence variants
Updated 2 months ago1
`riscv-rt`: Machine + Supervisor mixed executable
Updated 2 months ago1
`riscv-rt`: Broken eh_frame relocations on QEMU
Updated 2 months ago3
`riscv-rt`: Duplicate symbol when linking with Newlib
Closed 2 months ago1
`riscv`: align assembly functions with `cortex-m` crate
Updated 2 months ago1
`riscv-rt`: Prune unused symbols
Closed 3 months ago
`riscv-rt`: Pre initialization trap handling
Closed 3 months ago2
`riscv-rt`: Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing)
Updated 3 months ago1
`riscv-peripheral`: add standard peripherals
Updated 4 months ago12
`riscv-rt`: Using this as a library?
Closed 4 months ago5
Why are `asm::fence` and `asm::fence_i` unsafe?
Closed 4 months ago1
`riscv-rt`: LLVM raises spurious errors in release mode for instructions of ISA extensions (e.g., M or E)
Updated 4 months ago5
`riscv-rt`: nightly builds fail with `single-hart` feature: linker needs `default_mp_hook` symbol
Closed 4 months ago
`riscv-rt`: Can you have two versions in the build tree at the same time?
Closed 5 months ago1
Release time
Closed 5 months ago2
`riscv`: `interrupt::free()` for Supervisor Mode
Closed 5 months ago1
`riscv-rt`: Implement FPU initialization
Closed 5 months ago14
`riscv-rt`: Linker relocation issue (QEMU / OpenSBI)
Updated 6 months ago3
`riscv`: Add missing CSR's
Updated 6 months ago
FCSR operations generally cannot be used from Rust
Closed 7 months ago2
RVXXI registers
Closed 8 months ago2
Replace bors with GitHub merge queues
Closed a year ago2
`sip` register set / clear functions
Closed a year ago4
create a release for the atomicity things
Closed 2 years ago1
RISCV sdk with RUST support
Closed 2 years ago3
tag the 0.9.0 release
Closed 2 years ago1
The `critical_section` implementation is wrong
Closed 2 years ago3
Why are bare-metal and embedded-hal dependencies of this crate?
Closed 2 years ago1
The MTIP bit in mip register is read-only
Closed 2 years ago1
Support for riscv32imc.
Closed 2 years ago6
Implementing PMP registers as an array?
Closed 2 years ago2
"cannot link object files with different floating-point ABI" rustc 1.56.0-nightly (2021-08-06)
Closed 3 years ago2
linking with `rust-lld` failed: no memory region specified for section '.eh_frame', on Ubuntu 16 i686
Closed 3 years ago9
"cannot link object files with different floating-point ABI" (nightly-2021-03-23)
Closed 3 years ago1
Supervisor level ISA (Page system) support
Closed 4 years ago1
Mcounteren Missing
Closed 4 years ago2
How to use mcause::read()
Closed 4 years ago2
Set Stack Pointer and Return Address
Closed 4 years ago4
rust cross compile to riscv64gc
Closed 5 years ago2
move plic definition to riscv crate
Closed 5 years ago3
Raw instruction functions are unsafe footguns
Closed 5 years ago6
Failure to build due to unreachable code
Closed 6 years ago1