Rishiyur S. Nikhil's repositories
Forvis_RISCV-ISA-Spec
Formal specification of RISC-V Instruction Set
Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
ICFP2020_Bluespec_Tutorial
Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
RISCV_ISA_Spec_Tour
Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
RISCV_Piccolo_v1
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
Learn_Bluespec_and_RISCV_Design
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
RISCV_ISA_Formal_Spec_in_BSV
A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
Bluespec_BSV_Formal_Semantics
Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
Book_BLang_RISCV
Book to (1) learn BLang (BSV) using a RISC-V example and (2) learn to design a pipelined RISC-V CPU using BSV for HDL coding
goParseBSV
A standalone parser for BSV (Bluespec SystemVerilog) written in Go
Enigma_Cryptol_Bluespec_BSV
Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV
Tutorial_at_HPCA-29
An AWS-FPGA Testbed for Architecture Research on RISC-V CPUs, Accelerators, and Memory Systems
Multithreaded_Architectures_1993
Slides from Multithreaded Architectures tutorial 1993 by Rishiyur S. Nikhil
Experimental_RISCV_Feature_Model
An experimental DSL to describe the full feature list of a RISC-V implementation, along with constraints on features and between features
sail-riscv
Sail RISC-V model
Misc_Utilities
Miscellaneous Utilities
Temporary_TGISA
Temporary work site for another project (please ignore until public announcement)