rrotaru / CS385-CPU

CPU designed in Verilog

CS385-CPU

CPU designed in Verilog

###Task Format

Task

• SubTask - [Contributor 1], [Contributor 2], etc

Progress Report 1

Tasks

Template CPU File

• CPU Template - Rob, Tony

Extended ALU (16-bit)

• 16-bit ALU – Rob
  • Testing – Rob
• Gate Level 4x1 and 2x1 Mux – Bryan
  • Testing – Bryan

Register File (16-bit)

• 16-bit Registers – Bryan, Tony
  • 16-Bit Estension - Tony
  • 16-Bit D-Flip-Flops - Bryan
  • Testing - Tony
• Gate Level 4x1 Mux – Bryan
  • Testing – Bryan

Test Program (16-bit)

• 16-Bit Translation – Bryan
• Testing – Tony, Rob

Diagrams

• Single-Cycle Datapath - Tony
• Internals - Bryan

Report - Robert Rotaru, Bryan Bigelow, Anthony Cerritelli

Progress Report 2

Tasks

16-Bit Extended Test Program

• Assembly - Bryan
• Binary - Bryan

Data Memory

• Memory Modules - Rob, Tony
• SW/LW Instructions - Bryan, Rob, Tony

Branching Logic

• BNE/BEQ Instructions - Bryan, Rob, Tony
• Branching Modules - Rob, Tony

Diagrams

• Single-Cycle Path - Tony
• Internals -

Report - Robert Rotaru, Bryan Bigelow, Anthony Cerritelli

Progress Report 3

Tasks

3-Stage Pipelined Datapath

• Datapath for R-type and addi instructions - Tony

Tests

• Pipeline hazards - Tony

Diagrams

• 3-Stage pipeline - Bryan
• Internals -

** Report ** - Robert Rotaru, Bryan Bigelow, Anthony Cerritelli