robin's repositories
systemrdl-compiler
Tool to generate synthesizable RTL files from SystemRDL input
JSON2RTLRegFile
Generate RTL/Doc files from register description in JSON
Algos
Implementation of well-known (and some rare) algorithms, mostly in C++
Language:C++MIT000
Language:C000
ghdl
VHDL 2008/93/87 simulator
Language:VHDLGPL-2.0000
neomake
Async :make and linting framework for Neovim/Vim
Language:VimLMIT000
OSVVM
Open Source VHDL Verification Methodology (OSVVM) Repository
Language:VHDL000
vcdvcd
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line viewer.
Language:PythonNOASSERTION000
VHDL-indent-93-syntax
Revised VHDL indent file
Language:VimL000
VHDLComp
Vim Plugin to convert VHDL entity to component, signals or instantiations
Language:Python000
vim-snippets
vim-snipmate default snippets (Previously snipmate-snippets)
Language:PythonMIT000