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svd2rust

Generate Rust register maps (`struct`s) from SVD files

Language:RustApache-2.068100

rhdl

A Hardware Description Language based on the Rust Programming Language

Language:RustMIT9200

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Language:Tcl79500

riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Language:PythonCC-BY-4.04100

svlint

SystemVerilog linter

Language:RustMIT29900

svd

A CMSIS-SVD file parser

Language:RustApache-2.07000

sifive-core

Low level access to SiFive RISC-V processor cores

Language:RustNOASSERTION500

yosys

Yosys Open SYnthesis Suite

Language:C++ISC334600

ghdl

VHDL 2008/93/87 simulator

Language:VHDLGPL-2.0230500

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Language:CNOASSERTION23000