rithan2001

GRE-materials

https://github.com/AmoghDabholkar/GRE_PREP

Database-to-shortlist-Universities_VLSI-only-

How to shortlist universities for MS in US?

N-bit-Barrel-shifter

Bluespec sv coding

32-Bit-Barrel-shifter

Bluespec sv coding

Adders-in-bluespec-sv

AXI-protocal

shakti processor

Bluespec-bsc-codes

Licenced by IITM

Computer-Organisation

Gesture-controlled-robot

Bot movements are controlled by hand gesture

Real-time-clock-using-RTC-module

Real time clock using I2C Protocal and display time in serial moniter using uart communication

Computer-organisation-materials-

Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

heartrate_analysis_python

Python Heart Rate Analysis Package, for both PPG and ECG signals

IITM-Summer-intern

AXI Protocol

Image-Enhancement-Techniques

This primarily focuses on techniques for low-light images

IOT-based-PIR-motion-sensor

IOT-Gas-sensor

List-of-all-Research-Internship-Program-for-IIT-and-NITs

This contains the list of almost all the internship available for IIT and NIT students

macro_split

macronutrient split

Master-xdc-file

xilinx master constraints file of all digilient fpga board ,zynq board

Multiplier-Array-Booth-Wallace

Multipliers-in-Bluespec-sv

openlib.cs

📚 A Collection of Free & Open Resources for University Coursework in Computer Science.

Synthesizable-Verilog-Documentary

System-Verilog-

Udemy

Undergraduate-Internship-details

VLSI-CAD-Part-1-Logic

VLSI-CAD-Part-2-Layout

Wireless-Game-controller-using-IR-Data-Transmission

Xilinx-Zynq-7000-SoC-ZC702

Zynq 7000 ZC 702 schematic design , datasheet, user manual, master xdc file