Rishub's repositories
ascon-verilog-sca
Verilog Hardware Design of Ascon v1.2 with power side-channel mitigations
ascend-freepdk45
A free standard cell library for SDDS-NCL circuits
bluelight
Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
dotfiles
I wonder what's in here
flecs
A Multithreaded Entity Component System written for C89 & C99
gohugo-theme-ananke
Ananke: A theme for Hugo Sites
hugo-book
Hugo documentation theme as simple as plain book
hugo-geekblog
Hugo theme made for blogs
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
kickstart.nvim
A launch point for your personal nvim configuration
libdns
Core interfaces for universal DNS record manipulation across providers
lowrisc-toolchains
UNSUPPORTED INTERNAL toolchain builds
LWC
Development Package for the Hardware API for Lightweight Cryptography
netlistsvg
draws an SVG schematic from a JSON netlist
phobos
The standard library of the D programming language
rtFFT
real time FFT visualizer
SCALib
Side-Channel Analysis Library
TKGraphicsWrapper
OpenTK graphics wrapper
veersualize
Qt based visualization for the VeeR RISC-V core [WIP]
vivado-docker
Dockerfile with Vivado for CI
vivado-lxc
Launch an Ubuntu lxc container and install Xilinx Vitis/Vivado
xeda
Simulate And Synthesize HDLs!