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riscv / riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

Home Page:https://jira.riscv.org/browse/RVG-122

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Comments on version 94.60 (pdf)

PardoIlan opened this issue · comments

commented
  1. The encoding of max and minu have been flipped (changed between v0.92 and 0.93) - Is it intentional? Seems there was a change in the instructions name order in the table which was not done on the encoding.
  2. The encoding of rori for RV64 bit mode is different from that in RV32. It was the same in 0.93 and before - Is this change intentional?
  3. The source operand which get zero extended was changed from rs2 in v0.92 to rs1 (consistent with as slli.uw) between v0.92 and v0.93 - Is this intentional? I guess yes.

Thank you

commented

1 and 3 are deliberate, and were discussed on the mailing list. These were to make the instruction encodings more consistent with other extensions, and hence simpler to decode.

2 I hadn't seen before and looks odd.

commented

Thanks for the prompt response

commented

2 is similar to what has been also discussed in #146 : this change makes the size of the shamt-field and the undefined-instruction handling on RV32 explicit (i.e. only 5 bits of shamt can be encoded).