riscv / riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

Home Page:https://jira.riscv.org/browse/RVG-122

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zext.w missing from zbb table

jim-wilson opened this issue · comments

The table at the beginning of chapter 2 which lists all of the instructions in each subset doesn't mention zext.w for zbb. It is supposed to be in there. It is an alias of add.uw which is zba, but the subset that provides zext.w is in zbb. Just like zext.h in zbb is an alias for pack/packw even though pack/packw are not in zbb.

The idea here is that the base architecture plus zbb is supposed to provide a complete set of [sz]ext.[bhw] instructions. This set is not complete unless we have zext.w for rv64.

zext.w is already mentioned in multiple places in the document as an alias for add.wu. I thought we had agreement that the zext.w subset of add.wu would be part of zbb, but Andrew Waterman tells me it isn't. Oh well. This means that I plus zbb has 5 of the 6 possible [zs]ext.[bhw] instructions, and you need I plus zbb+zba to get all 6 of them. But anyone sensible should be implementing zbb+zba anyways, so we can live with that. In the short term, we have a few broken toolchains floating around, because the toolchain folks thought that zext.w was in zbb, but this will be a temporary problem.

Oops, the current implementation in gcc is generating zext.w for zbb or zba, seems like it should fix...

Maybe slli.uw for imm = 0 instruction should be the alias for zext.w and in zbb.
IIUC it is preferred to special case an immediate over special casing rs1 or rs2 == zero.

Or maybe it is not too late to include the whole slli.uw instruction in Zbb, so that with just I + Zbb you can do sensible unsigned index -> address computation even if you don't want to implement the fused slli.uw + add
of Zba (but as Jim rightly remarks, implementing Zba is the sensible thing to do).