riscv / riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

Home Page:https://jira.riscv.org/browse/RVG-122

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sll.uw alias for slli.uw

jim-wilson opened this issue · comments

In the base ISA, rv32i, we allow sll to accept either a register or an immediate as the shift count. sll with an immediate shift count is an alias for slli. It was suggested that for consistency, we should allow sll.uw as an alias for slli.uw.

Is this still relevant for 1.0.0?
We don't list any pseudos/aliases there (in fact these were all removed following the consensus from the early reviews) — but we could start a separate section for them....