Li Xinbing's repositories
SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
verilog-divider
a super-simple pipelined verilog divider. flexible to define stages
rv32m-multiplier-and-divider
a multiplier÷r verilog RTL file for RV32M instructions
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs