RipperJ / VerilogExpr2NAND-NOR

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

VerilogExpr2NAND-NOR

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

Introduction

This is one of the course project materials for HKUST-GZ MICS 6000H Logic Design Automation of Digital Systems. This project is alive, maintained by [e-mail]. Any discussion or suggestion would be greatly appreciated!

Requirements

• Python 3.9
  • ply 3.11
  • graphviz 0.20.1
  • logging 0.5.1.2
  • pyeda 0.28.0
• Vivado 2020.2
  • GUI is not required. Only using the standalone simulation commands. Details shown in runsim.sh
    • xvlog
    • xelab
    • xsim

Workflow

• Front-end:
  • lex (lexer)
  • yacc (parser)
• Middle-end
  • 2-level AND/OR logic minimization with ESPRESSO (with pyeda package)
  • NAND/NOR minimization
• Back-end
  • Verilog code generation
  • testbench generation

How to Run

• Step 0: ./clean.sh
  • Clean all cached files, and make sure the tool is not using outdated intermediate results. (Although our tool would overwrite intermediate files in most cases, this is a safer choice.)
• Step 1: Make sure you have a valid Verilog expression in test.v
  • We currently only support the following operators
    • BITWISE_AND: "&" : bitwise AND (binary) / reduction AND (unary)
    • BITWISE_OR: "|" : bitwise OR (binary) / reduction OR (unary)
    • BITWISE_NEG: "~" : bitwise NEG (unary) [returns the complement of a variable]
    • LOGICAL_AND: "&&": logical AND (binary)
    • LOGICAL_OR: "||": logical OR (binary)
    • LOGICAL_NEG: "!" : logical NEG (unary) [returns a single bit]
• Step 2: python main.py test.v
  • This step generates the following files, including NAND/NOR implementation and the testbench.
    • func.v: self-defined format -- "NAND g0(in1, in2, out);"
    • func_vivado.v: format accepted by Vivado simulation tools -- "nand g0(out, in1, in2);"
    • sim_func.v: testbench, end-to-end exhaustive comparison between (1) the NAND/NOR impl and (2) the original Verilog expr.
• Step 3: ./runsim.sh
  • This step triggers the simulation flow and gives standard output in the terminal.

Testcases

• We here provide some examples of Boolean expressions for test. You can write any expression as long as the operators are supported, and paste into test.v, then python main.py test.v to run the program.
  1. ~(!a | b)
  2. b | (b&c)
  3. a | !a & b
  4. ~(a&b)
  5. !(c || d)
  6. a&b&c | (a&b&!d) | (a&b&~e)
  7. a & ~a
  8. a || ~a
  9. a & (b || ~b)
  10. ~a & (b || ~b)
  11. A & B & C
  12. A | B | C
  13. a|||b
  14. ~a & ~b & ~c | ~a & ~b & c | a & ~b & c | a & b & c | a & b & ~c
  15. (!a || (a && b) || (a && c) || (b && !c)) && ~b | | 1'h0 & &c
  16. ~a & b & c | ~d | ~b & d | a & d & c

NAND/NOR 123

• NAND logic:
  • ~/!: NOT(A) -> A NAND A
  • &/&&: A AND B -> (A NAND B) NAND (A NAND B)
  • |/||: A OR B -> (A NAND A) NAND (B NAND B)
  • &/|(reduction)-> A [itself]
• NOR logic:
  • ~/!: NOT(A) -> A NOR A
  • &/&&: A AND B -> (A NOR A) NOR (B NOR B)
  • |/||: A OR B -> (A NOR B) NOR (A NOR B)
  • &/|(reduction)-> A [itself]

References and Interesting Links

• Documents:
  • PLY Document
  • Python EDA (pyeda) Document
    • pyeda Formal Equivalence Checking
  • Draw Logics with Python
  • AMD Xilinx Vivado Logic Simulation Docs
• Blogs:
  • A Quick Tutorial on Using Vivado Logic Simulation Tools
  • NAND-Only Circuit Implementation (geeks-for-geeks)
• Webpages Intros:
  • Verilog Operators
  • From 3-input NAND to 2-input NAND gate
  • wiki NAND logic and wiki NOR logic
• Slides:
  • From SOP/POS (DNF/CNF) to NAND/NOR implmentation
  • NAND/NOR Impl, by Ali Mustafa
• GitHub links:
  • Quine McCluskey (Tabulation) Method in Python/C++
  • Espresso Logic Minimizer
• Online tools:
  • Online Verilog Simulator
  • Boolean Expr Calculator (including NAND/NOR)