Rikus Honey's repositories
verilog-to-superconducting
A framework for SFPGA architecture exploration
abc_cmake
ABC: System for Sequential Logic Synthesis and Formal Verification
Language:CNOASSERTION000
dots
My dotfiles
Language:ShellMIT000
JoSIM
Superconductor Circuit Simulator
Language:C++MIT000
ngspice-mirror
Unofficial mirror of https://git.code.sf.net/p/ngspice/ngspice
Language:CNOASSERTION000
llhd
Low Level Hardware Description — A foundation for building hardware design tools.
Apache-2.0000
mise
dev tools, env vars, task runner
MIT000
moore
A hardware compiler based on LLHD and CIRCT
Apache-2.0000
pyo3
Rust bindings for the Python interpreter
NOASSERTION000
rikushoney
GitHub readme
000
rikushoney.com
Personal website
Language:HTMLMIT000
rpi-rpm
Remote power management with a Raspberry Pi
Language:PythonMIT000
rsfq_mitll_pdk
MIT-LL SFQ5ee Cell Library
Language:PythonGPL-3.0000
vts
A framework for SFPGA architecture exploration
Language:RustApache-2.0000
yosys_cmake
Yosys Open SYnthesis Suite
Language:C++ISC000