riccardodesanti / logic-networks-project

Final assignment of Logic Networks course project at Politecnico di Milano

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logic-networks-project

Final assignment of the Logic Networks course at Politecnico di Milano, year 2019-2020.

The project objective has been to model and implement the behavioural level of a Finite State Machine (FSM) that can encode information according to the Working-zone Encoding. For more information check this out.

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Final assignment of Logic Networks course project at Politecnico di Milano


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Language:VHDL 100.0%