rggen / rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

https://github.com/rggen/rggen

Import RTL output component

taichi-ishitani opened this issue 5 years ago · comments

Taichi Ishitani commented 5 years ago

Import RTL output component from the original implementation.

RTL::Item
- will be renamed SystemVerilog::FeatureRTL
RTL::Component
- will be renamed SystemVerilog::Component