DUH support
drom opened this issue · comments
Great project.
We are developing a new format named DUH. It can capture register information.
Would you be interested in adding D∪H format support?
more info
Hi @drom ,
Thank you for your opening this ticket !
I'm interested in supporting DUH format to increase number of users.
I looked int to the sample JSON file and I think its format is very simple.
Therefore, I think it is not difficult to create a loader component for DUH format.
I have some questions about DUH format.
- Is JSON5 different from JSON?
- What access type does DUT support?
- read-write/read-only/write-only?
- How about other access types such as W1C (write 1 to clear/read only) ?
- RgGen does not support parameterized register width and bit field width.
- Can you accept the limitation that these values should be constant value?
- Do other values which can be parameterized exist?
https://json5.org
https://github.com/bartoszkopinski/json5
access - https://github.com/sifive/duh-schema/blob/master/lib/primitive.js#L35
modifiedWriteValue - https://github.com/sifive/duh-schema/blob/master/lib/field.js#L6
fixed field width is fine.
@drom ,
Thank you for your update.
Can you give me the priority of this ticket?
I'm planning to update RgGen to introduce 'register file' layer.
If you're not in hurry I'd like to prioritize introducing 'register file' layer.
Hi @drom ,
I have a question.
https://github.com/sifive/block-pio-sifive/blob/36fbe0d07c599ce700b5471e511f64ddb06c15b0/docs/pio.json5#L103
In the above sample, width of register ODATA is set to pioWidth. How can I get actual value of pioWidth ? Is this a Verilog parameter?
yes, in the component, it is a constraint (in form of JSON schema). It will be passed down to the Verilog parameter.
The actual value will be decided at instantiation time.
Thanks. I understood.
One more question.
Is type of pioWidth expression of the register schema?
https://github.com/sifive/duh-schema/blob/86e26211117b514b18d006cbd0d6c4fe1931bee3/lib/register.js#L16
Yes, some of the register/field properties can depend on parameters.
Simple math expressions like a * 8 can be used to relate them to parameters.
I use https://mathjs.org/docs/expressions/ to parse expressions.
Thanks, I understood.
However, RgGen does not support parameterized bit width, register width, etc. because RgGen needs fixed these values to validate input register maps.
Hi @drom ,
I have questions.
https://github.com/sifive/duh/blob/master/docs/component.md#registers
In this example memoryMaps is a member of component.
https://github.com/sifive/block-pio-sifive/blob/master/docs/pio.json5
But in this example, it is a member of definition.
What is different between these memoryMaps.
Do you have an example DUH file including registerFIle items?
@drom ,
I have an additional question.
In the above PIO example, csrMemMap is used to describe register map but I found memoryMap but not csrMemMap from the duh-schema.
Is csrMemMap valid keyword?
https://github.com/sifive/duh/blob/master/docs/component.md#registers
In this examplememoryMapsis a member ofcomponent.
https://github.com/sifive/block-pio-sifive/blob/master/docs/pio.json5
But in this example, it is a member ofdefinition.
What is different between thesememoryMaps.
This is resolved by myself.
csrMemMap witnin definition is referred from memoryMaps within component.
@drom ,
What do modify value of modifiedWriteValue and modify value of readAction mean?
Default value of access/modifiedWriteValue/ReadAction:
sifive/duh#80
| RgGen bit field type | Support? | access | modifiedWriteValue | readAction | reserved |
|---|---|---|---|---|---|
| rw | yes | read-write | not specified | not specified | no |
| ro | yes | read-only | don't care | not specified | no |
| rof | no | no | |||
| wo | yes | write-only | not specified | don't care | no |
| rc | yes | read-only | don't care | clear | no |
| w0c | yes | read-write | zeroToClear | not specified | no |
| w1c | yes | read-write | oneToClear | not specified | no |
| rs | yes | read-only | don't care | set | no |
| w0s | yes | read-write | zeroToSet | not specified | no |
| w1s | yes | read-write | oneToSet | not specified | no |
| rwc | no | ||||
| rwe | no | ||||
| rwl | no | ||||
| rws | no | ||||
| w0crs | yes | read-write | zeroToClear | set | no |
| w1crs | yes | read-write | oneToClear | set | no |
| w0src | yes | read-write | zeroToSet | clear | no |
| w1src | yes | read-write | oneToSet | clear | no |
| w0trg | no | ||||
| w1trg | no | ||||
| w1 | yes | read-writeOnce | not specified | not specified | no |
| wo1 | yes | writeOnce | not specified | don't care | no |
| reserved | yes | don't care | don't care | don't care | yes |
Hi @drom ,
I just released initial version of DUH plugin for RgGen.
If you have enough time, can you try to use?