rchen (raymondrc)

raymondrc

Geek Repo

Location:Nanjing

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rchen's repositories

FPGA-SM3-HASH

Description of Chinese SM3 Hash algorithm with Verilog HDL

Language:VerilogLicense:MITStargazers:43Issues:2Issues:2

FPGA_SM4

FPGA implementation of Chinese SM4 encryption algorithm.

Language:VerilogLicense:GPL-3.0Stargazers:43Issues:2Issues:0

SM4-SBOX

Verilog Implementation of SM4 s-box

Language:VerilogLicense:GPL-3.0Stargazers:18Issues:2Issues:0

riscv-isa-extension-for-SM4

RISC-V instruction set extensions for SM4 block cipher

Language:CLicense:GPL-3.0Stargazers:17Issues:3Issues:0

CryptoHashAccelerator

Crypto Hash Accelerator

License:GPL-3.0Stargazers:3Issues:1Issues:0

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:2Issues:1Issues:0

Practical-Cryptography-for-Developers-Book

Practical Cryptography for Developers: Hashes, MAC, Key Derivation, DHKE, Symmetric and Asymmetric Ciphers, Public Key Cryptosystems, RSA, Elliptic Curves, ECC, secp256k1, ECDH, ECIES, Digital Signatures, ECDSA, EdDSA

Language:CSSLicense:MITStargazers:1Issues:1Issues:0

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

Language:SystemVerilogLicense:Apache-2.0Stargazers:1Issues:1Issues:0

scarv

SCARV: a side-channel hardened RISC-V platform

Language:ShellLicense:MITStargazers:1Issues:1Issues:0

theses

SCARV-related UG, PGR, and PhD thesis archive

License:MITStargazers:1Issues:1Issues:0

xcrypto

XCrypto: a cryptographic ISE for RISC-V

Language:MakefileLicense:MITStargazers:1Issues:1Issues:0