raulbehl

neuralNetwork

SRAM_SKY130

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

IHP-Open-PDK

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

OpenRAM

An open-source static random access memory (SRAM) compiler.

I2SRV64-SS-v1

Reconfigurable Computing Lab, DESE, Indian Institiute of Science

uvm-python-verification-lib

UVM Python Verification Agents Library

ish

Linux shell for iOS

verilog-eval

Verilog evaluation benchmark for large language model

sv-tutorial

SystemVerilog Tutorial

learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

riscv-simple-sv

A simple RISC V core for teaching

digitaljs_online

Online demonstration for DigitalJS

yosys2digitaljs

Export netlists from Yosys to DigitalJS

digitaljs

Teaching-focused digital circuit simulator

labs-with-cva6

Advanced Architecture Labs with CVA6

nebula

Nebula: a microarchitecture simulator built from loosely coupled microservices

100DaysOfRtl

I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.

VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

procyon

Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.

lizard

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

AutoSVA

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

verilog-utils

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

uvm-verilator

corundum

Open source FPGA-based NIC and platform for in-network compute

PY_UVM_Framework

This repo contain the PY-UVM Framework for different RISC-V Cores

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

rars

RARS -- RISC-V Assembler and Runtime Simulator

schoolRISCV

CPU microarchitecture, step by step

Practical-UVM-IEEE-Edition

This is the repository for the IEEE version of the book