rammber's repositories
aes-prefer1
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
awesome-python
A curated list of awesome Python frameworks, libraries, software and resources
rocket-chip
Rocket Chip Generator
SparrowRV
An embed RISC-V Core with RV32IM ISA named SparrowRV.
BrianHG-DDR3-Controller
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
awesome_list
😎 Awesome lists about all kinds of interesting topics
Computer-Science-Textbooks
Collect some CS textbooks for learning.
Tinyhttpd
Tinyhttpd 是J. David Blackstone在1999年写的一个不到 500 行的超轻量型 Http Server，用来学习非常不错，可以帮助我们真正理解服务器程序的本质。官网:http://tinyhttpd.sourceforge.net
FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
awesome-riscv
😎 A curated list of awesome RISC-V implementations
FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
DetectHumanFaces_prefer2
Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
awesome-time-series-analysis
This list collects learning resource, tools and dataset for time series analysis/time series data mining.
Python
最良心的 Python 教程：
bootstrap
The most popular HTML, CSS, and JavaScript framework for developing responsive, mobile first projects on the web.
FPGA-Build_prefer
A novel architectural design for stitching video streams in real-time on an FPGA.
tinyriscv
A very simple and easy to understand RISC-V core.
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
AHB-SRAMC
IC Verification & SV Demo
e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
git-study
a doce of git study
FPGA_ThreeLevelStorage
【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
awesome-python3-webapp-1
小白的Python入门教程实战篇：网站+iOS App源码→ http://t.cn/R2PDyWN 赞助→ http://t.cn/R5bhVpf