RAJESH KUMAR JHA's repositories
Retiming_Using_ML
Register manipulation algorithms which are in use today are heuristic based and they don’t provide the global optimum always. Here we aim to develop a machine learning algorithm that can solve the problem with greater speed and accuracy than the existing algorithms.
AI-Projects
Artificial Intelligence Projects
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C_Projects
Some interesting C based Projects
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FHL_Spring21
For the FHL
Github-Finder
First react project
ibit
InterviewBit solutions
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Verilog-to-Test-Bench-Converter
The code convert test bench file (.bench) to Verilog (.v) file.