qjj1212

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Verilog-Design-Examples

tbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

core_usb_cdc

Basic USB-CDC device core (Verilog)

verilog-mini-demo

Verilog极简教程

VerilogCodeECC

Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field

RegBuilder