Satan's disciples's repositories
AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
AXI-SDCard-High-Speed-Controller
A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
basic_verilog
Must-have verilog systemverilog modules
cdbus_ip
CDBUS Protocol and the IP Core for FPGA users
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
ebook-GPT-translator
Enjoy reading with your favorite style.
edalize
An abstraction library for interfacing EDA tools
FPGA-ftdi245fifo
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires 3 common IOs instead of additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
fxpmath
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
ISP-pipeline-hdrplus
Denoise,HDR,Isppipeline,Image-processing(图形处理),camera, Isp ,HDRplus
open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
opentitan
OpenTitan: Open source silicon root of trust
pp4fpgas-cn
中文版 Parallel Programming for FPGAs
PYNQ
Python Productivity for ZYNQ
qspiflash
A set of Wishbone Controlled SPI Flash Controllers
regif
A Register Interface tool
riffa
The RIFFA development repository
typer
Typer, build great CLIs. Easy to code. Based on Python type hints.
verilog-axis
Verilog AXI stream components for FPGA implementation
verilog-ethernet
Verilog Ethernet components for FPGA implementation
verilog-pcie
Verilog PCI express components
x393
mirror of https://git.elphel.com/Elphel/x393
Xilinx_Library
Vivado诸多IP，包括图像处理等
xkISP
xkISP：Xinkai ISP IP Core (HLS)
zynqmp_cam_isp_demo
ISP-Lite, VIP, MIPI-RX IP实现，测试平台为KV260+AR1335 3MP@30fps