pwang7

blue-rdma

RoCEv2 hardware implementation in Bluespec SystemVerilog

scripts

simple-tlb

AXI_spec_chinese

AXI协议规范中文翻译版

aya

Aya is an eBPF library for the Rust programming language, built with a focus on developer experience and operability.

BlueAXI4

BlueBasics

BlueStuff

A Bluespec SystemVerilog library of miscellaneous components

bsc

Bluespec Compiler (BSC)

bsv_lab_docs

Chainsaw

a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

connectal

Connectal is a framework for software-driven hardware development.

DeepL-Crack

Bypass 5,000 characters, Remove edit restriction, Use DeepL Pro Account Cookies/DeepL Api Free Token to translate, Unlock Formal/informal tone, Randomize fingerprint

DREAMPlaceFPGA

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit

fixSegfaultVCS

There is segmentation fault of VCS which should be fixed.

High-speed-UDP-transport-protocol

knitkit

mit-courses

Repository of course notes and homework

os-competition-info

RapidWright

Build Customized FPGA Implementations for Vivado

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

rw-jython

SpinalHDL

Scala based HDL

SpinalPlay

SpinalTemplateMill

SVA-AXI4-FVIP

YosysHQ SVA AXI Properties

svlint

SystemVerilog linter

vsdpcvrd

Performance characterization for VSD BabySoC comprising of RISC-V core, PLL and DAC

Xilinx-FPGA-PCIe-XDMA-Tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Xline