Puneet Goel's repositories
avst_adder
Example setup for UVM driven Icarus Verilog Simulation
avst_adder_vl
Reference eUVM testbench for verilator
bare-metal
bare-metal example code for arm,riscv
boolector
A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.
cmsgen
CMSGen, a fast uniform-like sample generator
crave
Constrained RAndom Verification Enviroment (CRAVE)
cryptominisat
An advanced SAT solver
dma_ip_drivers
Xilinx QDMA IP Drivers
dstep
A tool for converting C and Objective-C headers to D modules
goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
kode-mono
The Kode Mono Typeface @ Google Fonts
PeakRDL-euvm
Euvm plugin for SystemRDL's PeakRDL tool.
PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
RISC-V-Assembly-Language-Programming
Source Code
riscv-bare-metal
RISC-V bare metal on QEMU
riscv-hello-uart
Minimal bare-metal RISC-V assembly code with UART output for execution in QEMU
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv32-bare-metal-qemu
Bare minimum setup required to run bare metal riscv32 with qemu
serpentos.com
Primary website, statically generated using D